The present invention relates to processes for the fabrication of integrated circuit devices on semiconductor substrates, and in particular to processes by which self-aligned spacers in vertical gate DRAMs are formed.
A DRAM (dynamic random access memory) circuit usually includes an array of memory cells interconnected by rows and columns, which are known as wordlines (WLs) and bitlines (BLs), respectively. Reading data from or writing data to memory cells is achieved by activating selected wordlines and bitlines. Typically, a DRAM memory cell comprises a MOSFET (metal oxide semiconductor field effect transistor) connected to a capacitor. The transistor includes gate and diffusion regions which are referred to as either drain or source regions, depending on the operation of the transistor.
There are different types of MOSFETs. A planar MOSFET is a transistor where a surface of the channel region of the transistor is generally parallel to the primary surface of the substrate. A vertical MOSFET is a transistor where a surface of the channel region of the transistor is generally perpendicular to the primary surface of the substrate.
Trench capacitors are also frequently used with DRAM cells. A trench capacitor is a three-dimensional structure formed into a silicon substrate. This is normally formed by etching trenches of various dimensions into the silicon substrate. Trenches commonly have N+ doped polysilicon as one plate of the capacitor (a storage node). The other plate of the capacitor is formed usually by diffusing N+ dopants out from a dopant source into a portion of the substrate surrounding the lower part of the trench. Between these two plates, a dielectric layer is placed which thereby forms the capacitor.
To prevent carriers from traveling through the substrate between the adjacent devices, device isolation regions are formed between adjacent semiconductor devices. Generally, device isolation regions take the form of thick oxide regions extending below the surface of the semiconductor substrate. A sharply defined trench is formed in the semiconductor substrate by, for example, anisotropic etching. The trench is filled with oxide back to the surface of the substrate to provide a device isolation region. Trench isolation regions thus formed are called shallow trench isolation (STI) and have the advantages of providing device isolation regions across their entire lateral extent and of providing a more planar structure.
DRAM technology beyond the one hundred nanometer technology node requires the use of vertical MOSFETs to overcome the scalability limitations of planar MOSFET DRAM access transistors. Vertical MOSFETs allow the bit densities required for effective size reduction. However, the use of vertical MOSFETs is not yet widespread and several characteristics need to be optimized.
For example, as a result of increased gate conductor to bitline diffusion overlap area, total bitline capacitance may be larger with vertical MOSFETs than with conventional planar MOSFET structures. FIG. 1 is a cross-sectional view of a vertical MOSFET in which the vertical gate conductor 10 overlaps the entire depth of the bitline diffusion 20. Thus, MOSFET structure 10 includes trench top oxide layer 12, vertical gate polysilicon 14, gate conductor 16, gate nitride cap 18, bitline diffusion 20, storage node diffusion 22, and diffusion stud 24. The large overlap 26 of the vertical gate polysilicon 14 over the entire depth of the bitline diffusion 20 contributes to a larger total bitline capacitance with this vertical MOSFET than with a conventional planar MOSFET. Prior attempts to address this generally require that the depth of the bitline diffusion be minimized. However, minimization of bitline diffusion depth is complicated by the fact that integration requirements may dictate a relatively high thermal budget (i.e., bitline diffusion (BL) needing to be performed relatively early in the process).
An additional drawback of vertical MOSFETs is the occurrence of wordline to bitline diffusion shorts, also referred to as WL-BL shorts. The reason for increased wordline to bitline shorts is because the gate conductor 16 is connected to the vertical gate polysilicon 14 in the trench. This is illustrated in FIG. 2, where a prior art vertical MOSFET structure is shown with a misalignment between the edge of the gate conductor 16 and the edge of the deep trench. The misalignment causes the occurrence of WL-BL shorts, as indicated at 15. To prevent WL-BL shorts, the formation of spacers inside of the deep trench has been proposed in U.S. patent application Ser. No. 09/757,514 and U.S. patent application Ser. No. 09/790,011, both commonly assigned to the assignee. However, the present invention teaches the structure and method to form these spacers after formation of the STI and in a manner that reduces cost as compared to the methods of the previous art.
A method for forming a semiconductor memory cell array structure comprises providing a vertical MOSFET DRAM cell structure having a deposited polysilicon layer planarized to a top surface of a trench top oxide in an array trench of a silicon substrate; forming a shallow trench isolation oxide region along the array trench; etching the polysilicon layer selective to a nitride layer on the silicon substrate to form one or more silicon nitride spacers between a bitline diffusion region and a vertical gate polysilicon region, and between the shallow trench isolation oxide region and vertical gate polysilicon region; and depositing a gate stack structure over the vertical gate polysilicon region and between one or more silicon nitride spacers to form a borderless contact between the gate stack structure and bitline diffusion region, and shallow trench isolation oxide region. This invention is different from the earlier inventions disclosed in both U.S. patent application Ser. No. 09/757,514 and U.S. patent application Ser. No. 09/790,011, in the fact that the vertical gate polysilicon is not only isolated from the bitline diffusion by the nitride spacer, but also from the isolation oxide by the nitride spacer since the nitride spacer is formed after the shallow trench isolation (STI). This additional feature prevents electrical shorting of the vertical gate polysilicon from the direction of the isolation oxide.
A vertical MOSFET structure used in forming dynamic random access memory comprises a gate stack structure comprising one or more silicon nitride spacers; a vertical gate polysilicon region disposed in an array trench, wherein the vertical gate polysilicon region comprises one or more silicon nitride spacers; a bitline diffusion region; a shallow trench isolation region bordering the array trench; and wherein the gate stack structure is disposed on the vertical gate polysilicon region such that the silicon nitride spacers of the gate stack structure and vertical gate polysilicon region form a borderless contact with the bitline diffusion region and shallow trench isolation region.
The vertical MOSFET formed by this method features reduced vertical gate to top diffusion overlap capacitance (reduced bitline capacitance), and reduced incidence of bitline diffusion to vertical gate shorts (reduced incidence of WL-BL shorts).
The above described and other features are exemplified by the following figures and detailed description.